Welcome
About me:
I am a PhD student, currently pursuing my research on analog and mixed-signal circuits security under the guidance of Prof. Jiang Hu and Prof. JV Rajendran. Prior to joining TAMU, I was working on SoC emulation, ASIC prototyping platform development and FPGA design and board testing for base transceiver station based application.
LinkedIn: My Page
Research Interest:
Hardware Security
Education
Ph.D. in Computer Engineering, Texas A&M University, Texas, USA
M.S. in Microelectronics, Birla Institute of Technology and Science, Pilani, India, 2013
B.E. in Electrical and Electronics Engineering, Anna University, Chennai, India, 2010
Publications
[c2]. N. G. Jayasankaran, A. S. Borbon, A. Abuellil, E. Sanchez-Sinencio, J. Hu, and J. Rajendran, “Breaking Analog IC Locks via Satisfiability Modulo Theories,” International Test Conference, 2019 (Accepted). [c1]. N. G. Jayasankaran, A. S. Borbon, E. Sanchez-Sinencio, J. Hu, and J. Rajendran, “Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction,” IEEE/ACM International Conference on Computer-Aided Design, 2018.
Industry Experience
Worked in Wipro VLSI Services and Aricent Technologies for 6 years in the field of FPGA emulation and design/verification for the following clients: Nokia Siemens Networks, BULL (Atos) and Qualcomm.
Teaching Assistant Experience
  • Supported in preparing lab materials and grading for ECEN 759: Hardware Security, Spring 2018 and Fall 2018
  • Guided senior students for Capstone projects in ECEN 403/404: Electrical Design Lab I & II, Fall 2017
  • Conducted Cadence Virtuso labs for ECEN 714/474: Digital Integrated Circuit Design, Spring 2017
Awards
  • Richard Newton Young Student fellowship award to attend Design Automation Conference (DAC) 2018.
  • Received One Time Departmental Scholarship from the Electrical and Computer Engineering department, TAMU.
  • Annual Excellence Award from Aricent Technologies for automating the conversion of ASIC to FPGA RTL done at Qualcomm.
  • Feather on Cap award from Wipro VLSI Services for implementing the clock and reset synchronization strategy across multiple FPGAs in the ASIC prototyping project for BULL.
  • Excellence award and Feather on Cap awards from Wipro VLSI Services for the FPGA development work in the base transceiver station project for NSN.