ECEN 248 Introduction to Digital Systems Design

Fall 2014

Lab Webpage for Section 200, 501, 502, 503

 

News for submitting post-lab report:

 

Announcement:

1. Please read lab manuals prior to your regular lab time, and check if there is any deliverables such as a pre-lab report.

2. Grading Policy: 10% presence, 10% prelab, 20% report, 60% labwork. If there is no pre-lab, full scores of this part will be given.

3. The Lab report should contain the results of the experiments performed in the lab and any other deliverables mentioned in the lab manual.

4. Post-lab reports are due one week after the scheduled lab session unless specified. The reports should be submitted in the lab at the beginning of next lab session.

5. A deduction of 10% will be made per day after the deadline as the Late Submission Penalty.

6. Please hand in hardcopies. No softcopy of reports will be accepted.

 

Lab Sections:

Sections

Instructor

TA

Place

Day/Time

Date(MM/DD)

248-200

Dr. Jiang Hu

Chaofan Li

ZACH 115C

F 11:30 pm C 02:20 pm

09/01 - 12/17

248-501

Dr. Jiang Hu

Chaofan Li

ZACH 115C

T / 8:00 am C 10:50 pm

09/01 - 12/17

248-502

Dr. Jiang Hu

Chaofan Li

ZACH 115C

F / 8:00 am C 10:50 am

09/01 - 12/17

248-503

Dr. Jiang Hu

Ehsan Rohani

ZACH 115C

R / 2:20 pm C 5:10 pm

09/01 - 12/17

 

Teaching Assistant Details:

Name

Office Hour

Email

Office Addr

Chaofan Li

T / 1:00 pm C 2:00 pm

F / 2:30 pm C 3:30 pm

or by appointment

chaof@tamu.edu

321 WEB

Ehsan Rohani

W / 4:00pm C 5:00pm

or by appointment

ehsan.rohani@gmail.com

332A WEB

 

Class Website:

Class webpage for section 200, 501, 502, and 503.

 

General Materials:

- Laboratory Policies and Report Format

- Sample Lab report

- Data Sheets

 

Lab Schedule:

Dates

Lab #

Lab Content and Manual

Note

Sep.1 - Sep.7

0

None

 

Sep.8 - Sep.14

1

Digital Logic Gates

Component kits can be checked out at Zachry 111A, with TAMU IDs

Sep.15 - Sep.21

2

Inverter Characteristics and Ring Oscillator

 

Sep.22 - Sep.28

3

Logic Minimization with Karnaugh Maps

 

Sep.29 - Oct.5

4

Rudimentary Adder Circuits

 

Oct.6 - Oct.12

5

Simple Arithmetic Logic Unit

 

Oct.13 - Oct.19

6

Introduction to Logic Simulation and Verilog

two_one_mux_tb.v four_bit_mux_tb.v full_adder_tb.v four_bit_alu_tb.v add_sub_tb.v

Oct.20 - Oct.26

7

Introduction to Behavioral Verilog and Logic Synthesis

two_four_decoder_tb.v two_four_decoder.ucf four_two_encoder_tb.v four_two_encoder.ucf priority_encoder_tb.v priority_encoder.ucf

Oct.27 - Nov.2

8

Introduction to Sequential Logic

 

Nov.3 -  Nov.9

9

Counters, Clock Dividers, and Debounce Circuits

 

Nov.10 - Nov.16

10

An Introduction to High-Speed Addition

 

Nov.17 - Nov.23

11

A Simple Digital Combination Lock

 

Nov.24 - Nov.30

12 

The Traffic Light Controller Lab 

 

Dec.1 C Dec.7