ECEN 468 Advanced Digital System Design | Spring 2017
Lab webpage


TA: Chaofan Li
Email: chaof@tamu.edu
Office: WEB 321
Office Hour: Tuesday 3:00pm - 5:00pm or by appointment

Lab Time & Location

SessionTimeLocation
501Tuesday 5:30pm - 8:20pmCVLB 324
502Thursday 2:20pm - 5:10pmCVLB 324
503Thursday 5:30pm - 8:20pmCVLB 324

Announcements

1. If you do not have a UNIX account yet, please create your account here.
2. if the computers are Windows machines, download PuTTY here and use it to login your UNIX accout. Configure the PuTTY as shown here and here.
3. To download the files from the ECE server, you can search for a sftp client you like. For Windows, you can use WinSCP; For Linux, you can use sftp, scp or FileZilla.


4. The demo is due one week after the lab session. Please show the results (the waveform and/or run the program) to the TA in person.
5. Don't send the codes and waveforms to the TA's email. Include them in the lab reports.
Use $ source /softwares/setup/mentor/setup.vista312.linux.bash to load the configurations for vista.
Use $ source /softwares/setup/synopsys/setup.synopsys.bash to load the configurations for wv.
6. The VCS doesn't work on hera.ece.tamu.edu, however it works on apollo.ece.tamu.edu with the setup file I uploaded.
Login the apollo server by $ssh apollo.ece.tamu.edu
7. For lab 12, open the virtuoso by $ /softwares/setup/cadence/ncsu.bash

Lab Schedule

DatesLab #Lab ContentReference
01/17-01/20None
01/23-01/271SRAM (SystemC) RAM.cpp
test_RAM.cpp
01/30-02/032UART (SystemC) Lab2_code.tar.gz
UART_XMTR.cpp
UART_XMTR.h
main.cpp
test.cpp
test.h
02/06-02/103Connecting by Bus (SystemC) Lab3_code.tar.gz
Arbiter.cpp
Arbiter.h
SRAM_WRAP.cpp
SRAM_WRAP.h
UART_XMTR_WRAP.cpp
UART_XMTR_WRAP.h
main.cpp
test.cpp
test.h
02/13-02/174Canny Edge Detection (SystemC)Lab4_code.tar.gz
02/20-02/245Connecting Lab1 to Lab4Lab5_code.tar.gz
02/27-03/036Verificationtest_RAM.cpp
03/06-03/107SRAM (Verilog) Lab7_codeA.tar.gz
Lab7_codeB.tar.gz
new synopsys setup file for VCS
03/13-03/17Spring Break
03/20-03/248UART (Verilog)Lab8_code.tar.gz
03/27-03/319Connecting by Bus (Verilog)Lab9_code.tar.gz
04/03-04/0710Canny Edge Detection (Verilog)Lab10_code.tar.gz
04/10-04/1411Connecting Lab7 to Lab10Lab11_code.tar.gz
04/17-04/2112PLL

Grading Policies

1. There are no pre-lab reports in this lab. But, it is recommended that you read lab manual posted before you attend the regular lab. It will help you focus implementation during you are in the lab.
2. The lab report should include all of requirements in the lab manuals.
3. Please submit hardcopies of reports.
4. Lab reports are due one week after the scheduled lab session. The reports must be submitted in the lab at the beginning of the next lab session.
5. Late submission penalty : 20% of total score for one lab will be deducted on each subsequent weekday after the deadline.
6. Please submit your reports to TA directly.
7. (20%) Attendance, (40%) Lab works, (40%) Reports.