ECEN 454 Digital Integrated Circuit Design
Fall 2009
Lab Webpage
Section |
Instructor |
Lab Time |
Lab Location |
| 454-501 | Dr.Peng Li | F 09:00AM - 11:00AM | ZACH 213A |
| 454-502 | Dr.Peng Li | W 06:30PM - 08:30PM | ZACH 213A |
| 454-503 | Dr.Peng Li | F 11:20AM - 01:20PM | ZACH 213A |
Lab# |
Title |
Dates |
Files Required |
Points |
Report Due |
Report Due |
|
| Lab1 | Schematic Capture and Simulation | Sep 9 - Sep 11 | 10 | Sep 16 | Sep 18 | ||
| Lab2 | Layout and Extraction | Sep 16 - Sep 18 | 10 | Sep 23 | Sep 25 | ||
| Lab3 | Cell Characterization | Sep 23 - Sep 25 | cell18.spi, demo.spi, model18.spi | 10 | Sep 30 | Oct 2 | |
| Lab4 | Design and Simulation:1 bit adder | Sep 30 - Oct 2 | tsmc20P.m, tsmc20N.m | 10 | Oct 7 | Oct 9 | |
| Lab5 | Design and Simulation:4 bit adder | Oct 7 - Oct 9 | 10 | Oct 14 | Oct 16 | ||
| Lab6 | Optimization using Logical Effort | Oct 14 - Oct 16 | 10 | Oct 21 | Oct 23 | ||
| Lab7 | Design and Characterization of a FF | Oct 21 - Oct 23 | 10 | Oct 28 | Oct 30 | ||
| Lab8 | 8-bit pipelined adder with buffered H-clock tree | Oct 28 - Oct 30 | 10 | Nov 11 | Nov 13 | ||
| Lab9 | Logic Design using Verilog | Nov 11 - Nov 13 | VerilogRef Verilog Essentials |
10 | Nov 18 | Nov 20 | |
| Lab10 | Logic Synthesis and Static Timing Analysis | Nov 18 - Nov 20 | iit018_stdcells.db iit018_stdcells.lib | 10 | Dec 2 | Dec 4 | |
| Lab11 | Automatic Place and Route using Soc Encounter | Dec 2 - Dec 4 | iit018_stdcells.lef, iit018_stdcells.tlf, iit018_stdcells.lib, encounter.conf | 10 | Dec 9 | Dec 11 |